1. Field of the Invention
The present invention relates to a connection testing apparatus and method, and more particularly to a method of testing whether connection points of chips in a multi-chip package are truly connected by using a voltage variation caused by a current path.
2. Description of Related Art
With the advancement of science and technology, consumer electronics products are in more and more demand. In these days when motility and action ability are paid more attention to, a conventional large-scale tool providing powerful functions is gradually abandoned by people and replaced with a highly portable mobile electronic product with perfect functions. Some new-era products emerge as the times require, such as portable videodisc systems and mini personal computers. However, due to the significant addition of functions, the number of external electronic elements is greatly increased, such as memories and power module elements, and under such a circumstance that the size must be reduced but the number of elements is increased, each system company is engaged in a topic about reducing the size of circuit modules, and as a result, the technologies of Systems On Chip (SOC) and Systems In Package (SIP) have emerged correspondingly.
In response to the requirements of SIP, a multi-chip package becomes the first goal that should be challenged. In the current technology about the multi-chip package, the most difficult technique is the technique of mass production test. When chips with quite different functions are combined together, it is not difficult to test whether individual chips are normal; however, if it is intended to test whether each connection point of each chip is connected well, a conventional method is only to test it by using two chips in hand-shake. The method of conducting mass production test according to the relevant functions and actions of two or more chips should be completed by using a plenty of test patterns through a test machine. The test patterns prolong test time and cause a high test cost. High enough fault coverage cannot be guaranteed even if a functional test has been passed. Moreover, even if a chip with faults is tested, which kind of connection fault causes the functional fault cannot be determined accurately, which does not be favorable for the whole subsequent engineering analysis at all.